1. Field of the Invention
The present invention relates to alignment metrology, and in particular to an alignment target and method of use that includes two locations with designed in offsets.
2. Discussion of the Related Art
Semiconductor processing for forming integrated circuits requires a series of processing steps. These processing steps include the deposition and patterning of material layers such as insulating layers, polysilicon layers, and metal layers. The material layers are typically patterned using a photoresist layer that is patterned over the material layer using a photomask or reticle. Typically the photomask has alignment targets or keys that are aligned to fiduciary marks formed in the previous layer on the substrate. However, as the integrated circuit feature sizes continue to decrease to provide increasing circuit density, it becomes increasingly difficult to measure the alignment accuracy of one masking level to the previous level. This overlay metrology problem becomes particularly difficult at submicrometer feature sizes where overlay alignment tolerances are reduced to provide reliable semiconductor devices.
FIGS. 1A and 1B show conventional overlay targets used with conventional imaging metrology methods. FIG. 1A shows a typical Box-in-Box overlay target 2. Target 2 is formed by producing an etched box 4 in a material layer 6 on a substrate. A corresponding smaller box 8 on the photomask or reticle is aligned to the larger box 4 so that the centers of the large and small boxes are aligned.
FIG. 1B shows a Bar-in-Bar overlay target 12, which is similar to target 2 shown in FIG. 1A. Target 12 is produced by etching bars 14 in a material layer 16 on a substrate. The bars 18 on the photomask are aligned to the overlay target alignment bars 14.
After the smaller box 8 or bars 18 are developed, i.e., exposed and etched, the overlay target is imaged to determine whether the photomask or reticle was properly aligned with the underlying layer. Conventionally, high magnification imaging is used to measure overlay alignment. Conventional imaging devices, unfortunately, suffer from disadvantages such as sensitivity to vibration and cost. Moreover, conventional imaging devices suffer from a trade-off between depth-of-focus and optical resolution. Additionally, edge-detection algorithms used to analyze images for the purpose of extracting overlay error are inaccurate when the imaged target is inherently low-contrast or when the target suffers from asymmetries due to wafer processing.
Thus, there is a need in the semiconductor industry for improved alignment target and associated metrology.